1. Field of the Invention
The present invention relates to data flow type information processing apparatus. More particularly, the present invention relates to an information processing apparatus of a data flow type which performs operations upon arrival of data and which includes a program memory for storing data flow programs, provided outside a processing section.
2. Description of the Background Art
Conventional computers are for the most part von Neumann computers which store various instructions as programs in a program memory, access the instructions successively by sequentially designating addresses of the program memory by means of a program counter, and execute those instructions.
On the other hand, data flow type computers are of a type different from the von Neumann computers, which do not have the concept of sequential execution of instructions by using a program counter. Such a data flow type computer has an architecture in which instructions are processed in parallel, in principle. More specifically, whenever data to be processed is supplied, instructions can be executed and since a plurality of instructions are simultaneously executed on the data, the program can be executed in parallel according to the natural flow of the data. Thus, in such a data flow type computer, the time required for operation processing is considerably reduced.
FIG. 14 is a schematic block diagram of a conventional data flow type computer and FIG. 15 is an illustration showing part of contents stored in a program memory.
Referring to FIGS. 14 and 15, construction and operation of the conventional data flow type computer will be roughly described. In FIG. 14, a program storing portion 100 includes a program memory (not shown) which stores a data flow program including contents of destination fields of input data packets (destination information) and instruction information as shown in FIG. 15. The program storing portion 100 reads out the destination information and the instruction information by address designation based on the destination information, and stores respective information in a destination field and an instruction field of the input data packet so as to output the information.
A paired data detecting portion 200 queues data packets inputted from the program storing portion 100 and it stores operand data of one of the two data packets where a hit of destination information occurs, into a data field of the other data packet and outputs that operand data An operation processing portion 300 decodes instruction information of the data packet transferred from the paired data detecting portion 200, and performs predetermined processing for the two operand data, so that it stores the result in an input data field of the input data packet and outputs the result to the program storing portion 100.
In the data flow type information processing apparatus shown in FIG. 14, operation processing based on the program stored in the program storing portion 100 is performed while the data packets circulate in the program storing portion 100, the paired data detecting portion 200, the operation processing portion 300, the program storing portion 100 etc.
FIG. 16 is a diagram showing a schematic construction of the program storing portion shown in FIG. 14. In FIG. 16, an input data latch 101 maintains present destination information and instruction information is erased. The input data latch 101 also latches operand data. The destination information latched in the input data latch 101 is supplied to an address calculating portion 102 and an address of the program memory 103 is calculated based on the destination information. The program memory 103 stores the data flow program including the destination information and the instruction information as shown in FIG. 15. New destination information and instruction information read out from the program memory 103 are supplied to and latched at an output data latch 104. The output data latch 104 latches, as it is, the operand data latched in the input data latch 101.
In the above described conventional data flow type computer shown in FIGS. 14 to 16, the portions for reading out the instruction information of the program are all in the program storing portion 100 (which has been manufactured in advance and where it is impossible to add or remove any portions) and accordingly it is necessary to provide a memory having a capacity for storing all the programs. However, in general, it is difficult to provide an appropriate capacity for a program memory in a computer irrespective of whether it is formed by a plurality of semiconductor components or by a single LSI (large scale integration) chip, and a flexible hardware structure cannot be adopted according to the program to be executed.
Therefore, it may be considered to externally provide the program memory 103 for the program storing portion 100, thereby to suitably increase or decrease the capacity of the program memory 103. However, if the program memory 103 is externally provided, difficulty is involved as to how to access a cache memory contained in place of the program memory portions 102 and 103 and the external program memory 103.